Integrated circuit devices may generally be adapted to implement a wide array of functions. Programmable integrated circuit devices such as field programmable logic array (FPGA) devices may include configurable memory elements that may be used to implement different user designs. In general, such memory elements may be configured multiple times.
As an example, configuration random access memory (CRAM) bits in a programmable logic device may be overwritten when the device is being reconfigured. However, CRAM bits may be susceptible to single event upset (SEU) errors or unwanted changes. For instance, CRAM bits may be sensitive to external elements, such as radiation, that may inadvertently cause the affected CRAM bits to be corrupted.
In general, an integrated circuit device may include error detection circuitry that may be used to detect erroneous CRAM bits (e.g., CRAM bits that have been wrongly changed due to SEU errors). Often times, in order to correct any configuration error, the entire integrated circuit device (or more specifically, the configuration memory elements on the integrated circuit device) may need to be reconfigured.
Even though CRAM errors may be corrected by reconfiguring the device, reconfiguring the whole integrated circuit device is generally costly and time consuming as the device (and subsequently any system that the device may be used in) may need to remain inactive until it is fully reconfigured.
It is within this context that the embodiments described herein arise.